But i bet you if you try to write them on paper and do the logic xor manually you can easily understand whats going on in.Ħ-bit gray counter main entity is shown below. Important: The above logic is hard to explain. This next state is transferred to current state on next rising edge of clock. The current state is assigned to the output and next state is calculated. The result is placed in Nextstate variable Nextstate <= next_hold XOR (‘0’ & next_hold(N-1 DOWNTO 1)). In the third statement we perform the same concatenation and logical xor but this time on next_hold variable. The result is placed in next_hold variable next_hold <= std_logic_vector(unsigned(hold) + 1). In the next statement we increment the hold by 1. The result is placed in hold variable hold <= Currstate XOR (‘0’ & hold(N-1 DOWNTO 1)). We then xor this current state with the 5 lsb(least significant bits) of current state while concatenating the 0 at msb(most significant bit) of current state. I will give it a try.Īfter reset the current state value is 000000. I am sure its not possible for me to write the logic for those three code statements which you can pick up and easily understand. Well the code part after process is generating the next gray code value for us. How the gray counter is incremented in vhdl case? In the absence of clock you cant reset the system.Ĭoming to the main and complex logic. The reset is synchronous which means that reset execute on positive edge of the clock. These signals are used to hold the values manipulated for gray counter by finite state machine. In the architecture part few signals are defined. clock, reset and enable are 1-bit inputs. Notice that the output port size is dependent on the generic variable N. Clock, reset and enable signals are input to the entity and the only output is our gray code. You can change it according to your need. In my case i want a 6-bit gray counter so i initialized it with 6.
The generic variable is used to declare the size of the gray counter. In the main entity first a generic N: integer:=6 is defined. If you don’t know about finite state machine and how it works? Then before moving any future i will suggest you to first take some tutorials on fine state machine and how it works? I also assume that you are well aware of FSM(finite state machine). I assume that you now what is meant by current state and next state logic. The counter is designed on current and next state logic.
The main gray counter entity vhdl code is given below.
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